APPLICATIONS

l  1.25 Gigabit Ethernet over Cat 5 cable

COMPLIANCE

l  SFP MSA

l  INF-8074i

l  ROHS

l  CE

Ordering information

I.       Pin Definitions

Figure1. Pin out of Connector Block on Host Board

II.     Pin Descriptions

Notes:

Plug Seq.: Pin engagement sequence during hot plugging.

1) TX Fault is an open collector output, which should be pulled up with a 4.7k~10kΩ resistor on the host board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation; logic 1 indicates a laser fault of some kind. In the low state, the output will be pulled to less than 0.8V.

2) TX Disable is an input that is used to shut down the transmitter optical output. It is pulled up within the module with a 4.7 ¨C 10 K resistor. Its states are:

Low (0 to 0.8V):             Transmitter on

(>0.8, < 2.0V): Undefined

High (2.0 to 3.465V):         Transmitter Disabled

Open:                      Transmitter Disabled

3) Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a  4.7K to 10K resistor on the host board. The pull-up voltage shall be VccT or VccR

Mod-Def 0 is grounded by the module to indicate that the module is present

Mod-Def 1 is the clock line of two wire serial interface for serial ID

Mod-Def 2 is the data line of two wire serial interface for serial ID

4) LOS (Loss of Signal) is an open collector/drain output, which should be pulled up with a 4.7K to 10K resistor. Pull up voltage between 2.0V and VccT, R+0.3V. When high, this output indicates the received optical power is below the worst-case receiver sensitivity (as defined by the standard in use). Low indicates normal operation. In the low state, the output will be pulled to <0.8V.

5) RD-/+: These are the differential receiver outputs. They are AC coupled 100 differential lines which should be terminated with 100  (differential) at the user SERDES.

6) TD-/+: These are the differential transmitter inputs. They are AC-coupled, differential lines with 100 differential termination inside the module.

Table 1.+3.3V Volt Electrical Power Interface

The SFP-T has an input voltage range of +5V +/- 5%. The 3.3V maximum voltage is not allowed for continuous operation.

Caution: Power consumption and surge current are higher than the specified values in the SFP MSA

Table 2. Low-speed signals, electronic characteristics

MOD_DEF(1) (SCL) and MOD_DEF(2) (SDA), are open drain CMOS signals (see section VII, “Serial Communication Protocol”). Both MOD_DEF(1) and MOD_DEF(2) must be pulled up to host_Vcc.

Table 3. High-speed electrical interface, transmission line-SFP

All high-speed signals are AC-coupled internally.

Table 4. High-speed electrical interface, host-SFP

Table 5. General specifications

Notes:

1. Clock tolerance is +/- 50 ppm

2. By default, the SFP-T is a full duplex device in preferred master mode

3. Automatic crossover detection is enabled. External crossover cable is not required

4. 1000 BASE-T operation requires the host system to have an SGMII interface with no clocks, and the module PHY to be configured per Application Note AN-2036. With a SERDES that does not support SGMII, the module will operate at 1000BASE-T only.

III.   Environmental Specifications

IV.  References

1. Gigabit Interface Converter (SFP) Transceiver Multi-Source Agreement (MSA),

2. IEEE Std 802.3, 2002 Edition. IEEE Standards Department, 2002.

3. “AT24C01A/02/04/08/16 2-Wire Serial CMOS E2PROM”, Atmel Corporation.

4. “Alaska Ultra 88E1111 Integrated 10/100/1000 Gigabit Ethernet Transceiver”,Marvell Corporation.

V.     Mechanical Specifications

The host-side of the SFP-T conforms to the mechanical specifications outlined in the SFP MSA1. The front portion of the SFP (part extending beyond the face plate of the host) is larger to accommodate the RJ-45 connector.